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SP26LV432 High-Speed, Low-Power Quad RS-422 Differential Line Receiver
Quad Differential Line Receivers RI1B 1 Compatible with the EIA standard for 16 VCC RS-422 serial protocol RI1A 2 15 RI4B SP26LV432 High-Z Output Control R01 3 14 RI4A 14ns Typical Receiver Propagation Delays ENABLE 4 13 R04 60mV Typical Input Hysteresis 12 ENABLE R02 5 Single +3.3V Supply Operation 11 R0 RI2A 6 3 Common Receiver Enable Control 10 RI A RI2B 7 26LV32 industry standard footprint compatible 3 9 RI B GND 8 -7.0V to +7.0V Common-Mode Input 3 Voltage Range Switching Rates Up to 50Mbps Now Available in Lead-Free Packaging Ideal for use with SP26LV431 Quad Drivers DESCRIPTION The SP26LV432 is a quad differential line receiver with three-state outputs designed to meet the specifications of RS-422. The SP26LV432 features Sipex's BiCMOS process allowing low power operational characteristics of CMOS technology while meeting all of the demands of the RS-422 serial protocol at 50Mbps under load. The RS-422 protocol allows up to ten receivers to be connected to a multipoint bus transmission line. The SP26LV432 features a receiver enable control common to all four receivers and a high-Z output with 6mA source and sink capability. Since the cabling can be as long as 4,000 feet, the RS-422 receivers of the SP26LV432 are equipped with a wide (-7.0V to +7.0V) common-mode input voltage range to accommodate ground potential differences. TYPICAL APPLICATION CIRCUIT
ENABLE LOW HIGH HIGH Don't Care Don't Care HIGH Don't Care ENABLE HIGH Don't Care Don't Care LOW LOW Don't Care LOW Input don't care VID > VTH (max) VID < VTH (min) VID > VTH (max) VID < VTH (min) Open Open Output High-Z HIGH LOW HIGH LOW
VCC
RI A RI B 4 4
INPUTS
RI A RI B 3 3 RI A RI B 2 2 RI A RI B 1 1
ENABLE ENABLE
R04
HIGH
R03
R02
R01
GND
HIGH
OUTPUTS
Date: 04/27/06
SP26LV432 High Speed, Low Power Quad Differential Line Receiver
(c) Copyright 2006 Sipex Corporation
1
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device. VCC (Supply Voltage) ................................................................... +7.0V VCM (Common Mode Range) ........................................................ 14V VDIFF (Differential Input Voltage) .................................................. 14V VIN (Enable Input Voltage) ................................................... VCC + 1.5V TSTG (Storage Temperature Range) ........................... -65C to +150C Maximum Current Per Output .................................................... 25mA Storage Temperature .................................................. -65C to +150C Power Dissipation Per Package 16-pin PDIP (derate 14.3mW/C above +70C) ...................... 1150mW 16-pin NSOIC (derate 8.95mW/C above +70C) ..................... 725mW
ELECTRICAL CHARACTERISTICS
Unless otherwise noted, the following specifications apply for VCC = +3.0V to +3.6V with TAMB = 25C and all MIN and MAX limits apply across the recommended operating temperature range.
DC PARAMETERS Supply Voltage, VCC Enable Input Rise or Fall Times Input Electrical Characteristics Minimum Differential Input Voltage, VTH Input Resistance, RIN Input Current IIN IIN Minimum Enable HIGH Input Level Voltage, VIH(EN) Maximum Enable LOW Input Level Voltage, VIL(EN) Maximum Enable Input Current, IEN Input Hysteresis, VHYST Quiescent Supply Current, ICC Output Electrical Characteristics Minimum High Level Output Voltage, VOH Maximum Low Level Output Voltage, VOL Maximum Tri-state Output Leakage Current, IOZQ
MIN. TYP. MAX. UNITS 3.0 3 3.6 V ns
CONDITIONS
-200 5.0
50
+200
mV K
VOUT = VOH or VOL, -7V < VCM < +7V VIN = -7V, +7V, +10V other input = GND
+1.25 -1.5 2.0
+1.5 -2.5
mA mA V
VIN = +10V, other input = GND VIN = -10V, other input = GND
0.8 1.0 60 5 15
V A mV mA VIN = VCC or GND VCM = 0V VCC = +3.3V, VDIF = +1V VCC = +3.0V, VDIFF = +1V, IOUT = -6mA VCC = +3.0V, VDIFF = -1V, IOUT = +6mA VOUT = VCC or GND, ENABLE = VIL, ENABLE = VIH
2.4
2.8 0.2 0.5 0.5 5. 0
V V A
Date: 04/27/06
SP26LV432 High Speed, Low Power Quad Differential Line Receiver
(c) Copyright 2006 Sipex Corporation
2
SPECIFICATIONS (continued)
Unless otherwise noted, the following specifications apply for VCC = +3.0V to +3.6V, Tamb = 25C, tr < 6ns, tf < 6ns, and all MIN and MAX limits apply across the recommended operating temperature range.
MIN. TYP. MAX. UNITS AC PARAMETERS Propagation Delays Input to Output, tPLH, tPHL Output Rise and Fall Times, tRISE, tFALL Propagation Delay ENABLE to Output, tPLZ, tPHZ Propagation Delay ENABLE to Output, tPZL, tPZH 40 ns 40 ns 5 10 ns 14 35 ns
CONDITIONS
Refer to figure 2. CL = 50pF, VDIFF = 2.5V, VCM = 0V, VCC = +5V CL = 50pF, VDIFF = 2.5V, VCM = 0V, VCC = +5V CL = 50pF, RL = 1000, VDIFF = 2.5V, VCC = +5V Refer to Figure 4. CL = 50pF, RL = 1000, VDIFF = 2.5V, VCC = +5V
VCC
RI A RI B 4 4
INPUTS
RI A RI B 3 3 RI A RI B 2 2 RI A RI B 1 1
ENABLE ENABLE
R04 GND
Figure 1. SP26LV432 Block Diagram
R03
R02
R01
OUTPUTS
Date: 04/27/06
SP26LV432 High Speed, Low Power Quad Differential Line Receiver
(c) Copyright 2006 Sipex Corporation
3
RI1B RI1A R01 ENABLE R02 RI2A RI2B GND
1 2 3 4 5 6 7 8 SP26LV432
16 15 14 13 12 11 10 9
VCC RI4B RI4A R04 ENABLE R03 RI3A RI3B
PINOUT PIN DESCRIPTION
PIN NUMBER PIN NAME DESCRIPTION
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
RI1B RI1A R01 ENABLE R02 RI2A RI2B GND RI3B RI3A R03 ENABLE R04 RI4A RI4B VCC
Inverted RS-422 receiver input. Non-inverted RS-422 receiver input. TTL receiver output. Receiver input enable, active HIGH. TTL receiver output. Non-inverted RS-422 receiver input. Inverted RS-422 receiver input. Ground. Inverted RS-422 receiver input. Non-inverted RS-422 receiver input. TTL receiver output. Receiver input enable, active LOW. TTL receiver output. Non-inverted RS-422 receiver input. Inverted RS-422 receiver input. +3.0V to +3.6V power supply.
Date: 04/27/06
SP26LV432 High Speed, Low Power Quad Differential Line Receiver
(c) Copyright 2006 Sipex Corporation
4
AC TEST CIRCUITS AND SWITCHING TIME WAVEFORMS
VCC S1
+2.5V INPUTS (V-) - (V+) 0V -2.5V
tPHL tPLH tPLH tPHL
V+ INPUT DEVICE UNDER TEST RL
VOH 90% OUTPUT 50% VOL 10% tRISE tFALL 10% 90%
V- INPUT ENABLE ENABLE
CL
CL includes load and test jig capacitance. S1 = VCC for tPZL and tPLZ measurements. S1 = GND for tPZH and tPHZ measurements.
Figure 2. Propagation Delay
Figure 3. Test Circuit for high-Z Output Timing
ENABLE ENABLE
3.0V 1.3V GND
Differential Prop. Delay (ns)
16
1.3V
15 tPHLD
tPLZ VCC OUTPUT VOL VOH OUTPUT 0V tPHZ 0.5V 0.5V
tPZL 50%
14 tPLHD 13
50% tPZH
12
11
10 -40
-15
10
35
60
85
Temperature (C)
Figure 4. High Impedance Output Enable and Disable Waveforms
17
Figure 5. Differential Propagation Delay vs Temperature
2 1.8 tPHLD 1.6 1.4 1.2 1 0.8
16
Differential Prop. Delay (ns)
14
13
tPLHD
12
11 3.0
Differential Skew (ns)
3.4 3.5 3.6
15
3.1
3.2
3.3
0.6 -40 -15 10 35 60 85
Power Supply Voltage (V)
Temperature (C)
Figure 6. Differential Propagation Delay vs Supply Voltage
Date: 04/27/06
Figure 7. Differential Skew vs Temperature
(c) Copyright 2006 Sipex Corporation
SP26LV432 High Speed, Low Power Quad Differential Line Receiver
5
2.0 1.8 1.6
3.3 VCC = 3.3V 3.1
Output High Voltage (V)
Differential Skew (ns)
2.9 T = -40C
1.4 1.2 1.0 0.8
2.7
2.5 T = +25C 2.3 T = +85C
0.6 3.0 3.1 3.2 3.3 3.4 3.5 3.6
2.1 0 5 10 15 20
Power Supply Voltage (V)
Output High Current (mA)
Figure 8. Differntial Skew vs Supply Voltage
Figure 9. High Output Voltage vs Current over Temperature
1.6 1.4
3.6
3.2 VCC = 3.6V
1.2
VCC = 3.3V
T= +85C
Output High Voltage (V)
2.8 VCC = 3.3V VCC = 3.0V 2.0
Output Low Voltage (V)
1.0 0.8 0.6 0.4
T=+25C
2.4
T= -40C
1.6
0.2 0.0
1.2 0 5 10 15 20 25
0
5
10
15
20
Output High Current (mA)
Output Low Current (mA)
Figure 10. High Output Voltage vs Current over Supply Voltage
Figure 11. Low Output Voltage vs Current over Temperature
1.4 VCC = 3.0V 1.2 1.0 VCC = 3.3V 0.8 0.6 0.4
15 45
Output Low Voltage (V)
Input Resistance (K)
35
VCC = 3.6V
25
0.2 0.0 0 5 10 15 20
5 -10.0 -8.0
-6.0 -4.0
-2.0
0.0
2.0
4.0
6.0
8.0 10.0
Output Low Current (mA)
Input Voltage (V)
Figure 12. Low Output Voltage vs Current over Supply Voltage
Date: 04/27/06
Figure 13. Input Resistance vs Input Voltage
(c) Copyright 2006 Sipex Corporation
SP26LV432 High Speed, Low Power Quad Differential Line Receiver
6
0.9 +10V @ Inverting Input 0.6 0.3 +10V @ Non-Inverting Input
80 VHYST 60 VTH
Transition Voltage (mV)
Input Current (mA)
40
0.0 -0.3 -0.6
0V @ Inverting Input 0V @ Non-Inverting Input
20 VCC = 3.3V 0 VTL
-0.9 -1.2 3.0 3.1 3.2
-10V @ Inverting Input -10V @ Non-Inverting Input 3.3 3.4 3.5 3.6
-20
-40 -40
-15
10
35
60
85
Temperature (C)
Power Supply Voltage (V)
Figure 14. Input Current vs Supply Voltage
Figure 15. Transition Voltage vs Temperature
80 VHYST 60
7.0 VCC = 3.3V 6.5
Transition Voltage (mV)
20
Supply Current (mA)
VTL 3.0 3.1 3.2 3.3 3.4 3.5 3.6
40
6.0
5.5
0
5.0
-20
4.5
-40
Power Supply Voltage (V)
4.0 -40
-15
10
35
60
85
Temperature (C)
Figure 16. Transition Voltage vs Supply Voltage
Figure 17. Supply Current vs Temperature
7.0 6.5
5.4 VCC = 3.0V 5.1 50pF Load
Disabled Supply Current (mA)
6.0
Supply Current (mA)
5.5 5.0 4.5 4.0 3.5 3.0 3.0 3.1 3.2 3.3 3.4 3.5 3.6
4.8 1 TTL Load 4.5
4.2
No Load
3.9
3.6 1 10 100 1000 10000 100000
Power Supply Voltage (V)
Data Rate (kBaud)
Figure 18. Disabled Supply Current vs Supply Voltage
Date: 04/27/06
Figure 19. Supply Current vs Data Rate
(c) Copyright 2006 Sipex Corporation
SP26LV432 High Speed, Low Power Quad Differential Line Receiver
7
THEORY OF OPERATION The SP26LV432 is a low-power quad differential line receiver designed for digital data transmission meeting specifications of the EIA standard RS-422 protocol. The SP26LV432 features Sipex's BiCMOS process allowing low power operational characteristics of CMOS technology while meeting all of the demands of the RS-422 serial protocol to at least 50Mbps under load in harsh environments. The RS-422 standard is ideal for multi-drop applications and for long-distance communication. The RS-422 protocol allows up to ten receivers to be connected to a data bus, making it an ideal choice for multi-drop applications. Since the cabling can be as long as 4,000 feet, the RS-422 receivers have an input sensitivity of 200mV over the wide (-7.0V to +7.0V) common mode range to accommodate ground potential differences. Internal pull-up and pull-down resistors prevent output oscillation on unused channels. Because the RS-422 is a differential interface, data is virtually immune to noise in the transmission line. The SP26LV432 accepts RS-422 levels and translates these into TTL or CMOS input levels. The SP26LV432 features active HIGH and active LOW receiver enable controls common to all four receiver channels. A logic HIGH on the ENABLE pin (pin 4) or a logic LOW on the ENABLE pin (pin 12) will enable the differential receiver outputs. A logic LOW on the ENABLE pin (pin 4) and a logic HIGH on the ENABLE pin (pin 12) will force the receiver outputs into high impedance (high-Z). Refer to the truth table in Figure 20. The RS-422 line receivers feature high source and sink current capability. All receivers are internally protected against short circuits on their inputs. The receivers feature tri-state outputs with 6mA source and sink capability. The typical receiver propagation delay is 14ns (35ns max). To minimize reflections, the multipoint bus transmission line should be terminated at both ends in its characteristic impedance, and stub lengths off the main line should be kept as short as possible.
ENABLE LOW HIGH HIGH Don't Care Don't Care HIGH Don't Care
ENABLE HIGH Don't Care Don't Care LOW LOW Don't Care LOW
Input don't care VID > VTH (max) VID < VTH (min) VID > VTH (max) VID < VTH (min) Open Open
Output High-Z HIGH LOW HIGH LOW
*RT is optional although highly recommended to reduce reflection.
Driver Side such as SP26LV431 Receiver Side such as SP26LV432
ENABLE DATA OUTPUT
DATA
*RT
HIGH HIGH
Figure 20. Truth Table, Enable/Disable Function Common to all Four RS-422 Receivers
Figure 21. Two-Wire Balanced Systems, RS-422
Date: 04/27/06
SP26LV432 High Speed, Low Power Quad Differential Line Receiver
(c) Copyright 2006 Sipex Corporation
8
PACKAGE: 16 PIN PDIP
A1 D A N D1 b3 e b2 b L A2
INDEX AREA
E1 E
123
N/2
E
c eA eB
16 PIN PDIP JEDEC MS-001 (BB) Variation SYMBOL MIN NOM MAX A 0.21 A1 0.15 A2 0.115 0.13 0.195 b 0.014 0.018 0.022 b2 0.045 0.06 0.07 b3 0.3 0.039 0.045 c 0.008 0.01 0.014 D 0.735 0.75 0.755 D1 0.005 E 0.3 0.31 0.325 E1 0.24 0.25 0.28 .100 BSC e .300 BSC eA eB 0.43 L 0.115 0.13 0.15 Note: Dimensions in (mm)
b
C
Date: 04/27/06
SP26LV432 High Speed, Low Power Quad Differential Line Receiver
(c) Copyright 2006 Sipex Corporation
9
PACKAGE: 16 PIN NSOIC
D
e O E/2 E1 E1/2 E L2 Seating Plane 1 INDEX AREA (D/2 X E1/2) b O1 L1 L Gauge Plane O
TOP VIEW
VIEW C
A
A1 Seating Plane A2
SIDE VIEW
16 Pin NSOIC JEDEC MO-012 (AC) Variation MIN NOM MAX SYMBOL A 1.35 1.75 A1 0.1 0.25 A2 1.25 1.65 b 0.31 0.51 c 0.17 0.25 9.90 BSC D 6.00 BSC E 3.90 BSC E1 1.27 BSC e L 0.4 1.27 1.04 REF L1 0.25 BSC L2 o 0 8 o1 5 15 Note: Dimensions in (mm)
B
B
SEE VIEW C
b
c
BASE METAL
SECTION B-B WITH PLATING
Date: 04/27/06
SP26LV432 High Speed, Low Power Quad Differential Line Receiver
(c) Copyright 2006 Sipex Corporation
10
ORDERING INFORMATION
Model Temperature Range Package SP26LV432CP ............................................................................. 0C to +70C ..................................................................................... 16-pin PDIP SP26LV432CP-L ......................................................................... 0C to +70C ..................................................................................... 16-pin PDIP SP26LV432CN ............................................................................ 0C to +70C .................................................................................. 16-pin NSOIC SP26LV432CN-L ......................................................................... 0C to +70C .................................................................................. 16-pin NSOIC SP26LV432CN/TR ...................................................................... 0C to +70C .................................................................................. 16-pin NSOIC SP26LV432CN-L/TR ................................................................... 0C to +70C .................................................................................. 16-pin NSOIC
Available in lead free packaging. To order add "-L" suffix to part number. Example: SP26LV432CN/TR = standard; SP26LV432CN-L/TR = lead free /TR = Tape and Reel Pack quantity is 2,500 for NSOIC.
REVISION HISTORY
DATE 3/08/04 3/08/04 4/17/06
REVISION A B C
DESCRIPTION Production Release. Included tape and reel p/n. Fixed truth table typo pg1
SOLVED BY SIPEX
Sipex Corporation Headquarters and Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Date: 04/27/06
SP26LV432 High Speed, Low Power Quad Differential Line Receiver
(c) Copyright 2006 Sipex Corporation
11

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